Memory testing involves determining failed memory locations, typically by writing data to an array of memory locations, reading data from the memory locations, and comparing the read data to the data previously written. A memory can be tested using an external memory tester or a built-in self-test (BIST). An external memory tester has direct access to the memory's control, address, and data pins. As the memory is tested, the row address and the column address of each failed memory location are stored in the external memory tester. A BIST includes testing circuitry that is embedded in the memory to be tested. The BIST executes a set of algorithmic verification tests directly on the memory array.
A BIST scheme for testing a memory includes a “stop and resume” scheme. In the “stop and resume” scheme, the BIST suspends memory testing when an error is detected. After the incorrect test response is read from the BIST, the BIST resumes testing of the memory. The “stop and resume” scheme tests the memory at a speed that may be slower than the rated functional speed or intended operating speed of the memory and may not detect time-related errors that occur at the memory's rated functional speed. To test a memory for time-related errors, the memory is tested at the rated functional speed using a BIST scheme such as a “count” scheme. In the “count” scheme, the BIST gathers error information and increments a counter value when an error is detected. In successive test repetitions, the BIST does not gather error information until the number of errors surpasses the counter value. In the “count” scheme, the number of errors reported may be limited by the maximum counter value, and intermittent errors may interfere with the reporting of consistently repeatable errors.